The inventors of the present invention have proposed a sampling and holding circuit for analog voltages in Japanese Patent Application Hei No. 05-045900 (FIG. 13). This circuit uses two sets of 3 stage serial inverters for holding data with good accuracy.
This type of circuit has disadvantages of large circuit size because of the inverters required for each sampling and holding circuit, particularly in the technical field of image processing or voice processing, where a lot of data is parallelly processed along a time sequence or for two or more dimensions.
As shown in FIG. 13, this sampling and holding circuit has a) a sampling circuit S1 with an odd number of serial MOS inverters, the inputs and outputs of which are connected through a feedback capacitance with each other, b) a switch SW1 for connecting an input voltage of the sampling circuit through a coupling capacitance CC2 and c) a switch SW2 for connecting the sampling circuit S1 and the coupling capacitance CC2. The data is held by capacitances CF1, CF2, CC1 and CC2 as electrical charges.
The electrical charge may remain in the MOS inverters, or in the capacitances so as to cause an offset voltage. However, refreshment is needed to delete the offset by short circuiting the inputs and outputs of the sampling and holding circuits S1 and H1. This refreshment undesirably causes a refresh noise at the output of the sampling and holding circuit.